Transistor, fabricating method thereof and flat panel display therewith

ABSTRACT

A transistor includes a substrate, an active region including a source region, a channel region, and a drain region which are crystallized using an SGS crystallization method and are formed on the substrate so that a grain size of a first annealed portion and a second annealed portion are different from each other, a gate insulating layer formed on the active region, and a gate electrode formed on the gate insulating layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korean Application No.2006-138322 filed on Dec. 29, 2006, in the Korean Intellectual PropertyOffice, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Aspects of the present invention relate to a transistor, a fabricatingmethod thereof, and a flat panel display device therewith. Moreparticularly, aspects of the present invention relate to a transistor, afabricating method, and a flat panel display device, wherein anamorphous silicon layer formed on an insulating substrate iscrystallized into a polycrystalline silicon layer using an SGS (SuperGrain Silicon) crystallization method, whereby the substrate undergoes afirst annealing process by absorbing or diffusing an extremely smallamount of metal catalysts into a capping layer as the substrateundergoes a first heat treatment in order to control the concentrationof the metal catalyst left in the polycrystalline silicon layer, thenthe substrate undergoes a second annealing process, that is, a remainingcrystallization as the substrate undergoes a second heat treatment afterthe capping layer and the metal catalyst layer are removed.

2. Description of the Related Art

In general, a thin film transistor (TFT) is a semiconductor devicewherein a channel region, where a hole or an electron can flow, can beformed by doping a P-type or an N-type dopant on a source region and adrain region, and then applying a predetermined voltage to a gateelectrode. The thin film transistor can be classified into a PMOS(P-type metal-oxide semiconductor) transistor and an NMOS (N-typemetal-oxide semiconductor) transistor. If the source region and thedrain region are doped with the P-type dopant, and the hole flows when achannel region is formed, the transistor is called the PMOS transistor.On the contrary, if the source region and the drain region are dopedwith the N-type dopant, and the electron flows when a channel region isformed, the transistor is called the NMOS transistor.

The thin film transistor is used widely as a switching transistor or adriving transistor of a variety of flat panel display devices, such asan active matrix liquid crystal display device and an organic lightemitting diode display device. In general, in the thin film transistoras described above, amorphous silicon is deposited on a substrate madeof glass, quartz, plastic or steel. Then, a semiconductor layer isformed by crystallizing the amorphous silicon after the amorphoussilicon is dehydrogenated. Specifically, the semiconductor layer isformed by depositing an amorphous silicon layer on the substrate using achemical vapor deposition method, and processed to include a sourceregion, a drain region and a channel region (referred to as an activeregion as a whole).

However, if the amorphous silicon is deposited directly on a substrateby the chemical vapor deposition method and the like, the amorphoussilicon layer containing about 12% of hydrogen is formed, which has lowelectron mobility. In addition, if the amorphous silicon layer of lowelectron mobility is crystallized into a silicon layer with acrystalline structure having high electron mobility, the silicon layercan be damaged by an explosion of the hydrogen contained therein.Accordingly, a dehydrogenation process is executed in order to preventthe explosion of the hydrogen during the course of the crystallizationprocess.

In general, an amorphous silicon layer is dehydrogenated byheat-treating the amorphous silicon layer for dozens of minutes to a fewhours at temperatures over 400° C. in a furnace. Subsequently, acrystallization process to crystallize the dehydrogenated amorphoussilicon layer is carried out.

A few methods used to crystallize the amorphous silicon intopolycrystalline silicon include solid phase crystallization, excimerlaser crystallization, metal induced crystallization, and metal inducedlateral crystallization. The solid phase crystallization is a methodwherein an amorphous silicon layer is annealed for a few hours to dozensof hours below about 700° C. 700° C. is a deflection temperature ofglass which forms a substrate of a display device to which a thin filmtransistor is applied. An excimer laser crystallization is a methodwherein an amorphous silicon layer is heated locally to a hightemperature by injecting a light beam from an excimer laser into theamorphous silicon layer so that the amorphous silicon layer iscrystallized.

A metal induced crystallization is a method wherein a metal such asnickel, palladium, gold, aluminum, and so on, is brought into contactwith an amorphous silicon layer or injected into the amorphous siliconlayer. Consequently, a phase transition is induced during which theamorphous silicon changes into polycrystalline silicon. A metal inducedlateral crystallization is a method wherein silicide generated from thereaction of a metal and silicon continuously propagates laterally.Consequently, metal induced lateral crystallization induces thecrystallization of an amorphous silicon layer in sequence.

However, the solid phase crystallization has disadvantages in that theprocess time is too long, and the substrate can be deformed easily dueto the high temperature heat treatment occurring over a long time. Theexcimer laser crystallization has disadvantages in that the processrequires an expensive laser device, and the interfacial property betweena semiconductor layer and a gate insulating layer is poor becauseextrusions are generated on a polycrystallized surface. The metalinduced crystallization or the metal induced lateral crystallizationhave disadvantages in that a leak (or leakage) current of asemiconductor layer of a thin film transistor increases because metalcatalysts are left in the polycrystalline silicon layer. Consequently,the characteristics of various flat panel display devices using thesilicon layer as a switching transistor or a driving transistor of theabove processes are poor.

SUMMARY OF THE INVENTION

Aspects of the present invention are directed to controlling theconcentration of the metal catalyst left in a polycrystalline siliconlayer when an amorphous silicon layer formed on an insulating substrateis crystallized into a polycrystalline silicon layer using an SGS (SuperGrain Silicon) crystallization method.

An aspect of the present invention is to provide a transistor, afabricating method, and a flat panel display device, wherein a substrateis crystallized by absorbing or diffusing an extremely small amount ofmetal catalysts into a capping layer as the substrate undergoes a firstheat treatment. Subsequently, the substrate undergoes a remaining (orfurther) crystallization as the substrate undergoes a second heattreatment after the capping layer and the metal catalyst are removed.Accordingly, a leak (or leakage) current can be minimized because theconcentration of the metal catalyst left in the polycrystalline siliconlayer can be minimized.

A transistor according to an aspect of the present invention minimizes aleak (or leakage) current can include a substrate; an active regionincluding a source region, a channel region, and a drain region whichare crystallized using an SGS (Super Grain Silicon) crystallizationmethod and are formed on the substrate so that a crystal grain size of afirst annealed portion and a second annealed portion are different fromeach other; a gate insulating layer formed on the active region; and agate electrode formed on the gate insulating layer.

According to aspects of the present invention, a grain boundary size ofthe first annealed portion can be smaller than that of the secondannealed portion. The concentration of metal catalysts of the firstannealed portion can be higher than that of the second annealed portion.The source region and the drain region of the active region can be dopedwith either a P-type dopant or an N-type dopant. The gate electrode canbe one of MoW, Ti, Cu, AiNd, Al, Cr, Mo alloy, Cu alloy, Al alloy, orany combinations thereof. The transistor can also include a buffer layerformed between the substrate and the active region. The metal catalystcan be one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh,Cd, Pt, or any combination thereof.

The transistor according to an aspect of the present invention can alsoinclude an inter-layer dielectric layer formed on a surface of the gateinsulating layer and the gate electrode, a source electrode connected tothe source region and penetrating through the inter-layer dielectriclayer and the gate insulating firm, and a drain electrode connected tothe drain region and penetrating through the inter-layer dielectriclayer and the gate insulating layer.

A fabricating method of the transistor according to an aspect of thepresent invention includes preparing a substrate; forming an amorphoussilicon layer on the substrate; forming a capping layer on the amorphoussilicon layer; forming a metal catalyst layer on the capping layer;performing a first annealing process to crystallize amorphous silicon ofthe amorphous silicon layer into first annealed polycrystalline siliconusing an SGS (Super Grain Silicon) crystallization method wherein metalcatalysts of the metal catalyst layer diffuse as far as the amorphoussilicon by penetrating through the capping layer; removing the metalcatalyst layer and the capping layer; and performing a second annealingprocess wherein the metal catalyst crystallizes the amorphous siliconinto second annealed polycrystalline silicon using an SGScrystallization method to form a polycrystalline silicon layer.

In aspects of the present invention, after the second annealing process,the method can include forming a semiconductor layer (an active region)by patterning the polycrystalline silicon layer and forming a gateinsulating layer, a gate electrode, an inter-layer dielectric layer, anda source/drain electrode on the substrate. During removing of the metalcatalyst layer and the capping layer, the metal catalyst layer and thecapping layer may be removed once the size of the respective grainboundary size is smaller than half of an average distance between themetal catalysts as the amorphous silicon is crystallized.

In aspects of the present invention, the method can also include forminga buffer layer prior to the forming of the amorphous silicon layer onthe substrate. The crystallinity of the polycrystalline silicon formedby the first annealing process is different from that of thepolycrystalline silicon formed by the second annealing process. A grainboundary size of the polycrystalline silicon formed by the firstannealing process is smaller than that of the polycrystalline siliconformed by the second annealing process.

According to aspects of the present invention, the concentration of themetal catalyst of the polycrystalline silicon formed by the secondannealing process is lower than that of the metal catalyst of thepolycrystalline silicon formed by the first annealing process. The metalcatalyst layer can be one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo,Tr, Ru, Rh, Cd, Pt, or any combinations thereof. The capping layer canbe an insulating layer and be one of an oxide film, a nitride film, orany combinations thereof. The oxide film can be one of silicon dioxide(SiO₂), aluminum oxide (alumina, Al₂O₃), hafnium oxide (HfO₂) andzirconium oxide (zirconia, ZrO₂).

As described above, in aspects of the present invention, a leak (orleakage) current can be reduced by minimizing the concentration of themetal catalyst that is unnecessarily left in a polycrystalline siliconlayer. In addition, a polycrystalline silicon layer of excellent (orimproved) crystallinity can be obtained by reducing unnecessarycrystallization by remaining metal catalysts.

Additional aspects and/or advantages of the invention will be set forthin part in the description which follows and, in part, will be obviousfrom the description, or may be learned by practice of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the invention will becomeapparent and more readily appreciated from the following description ofthe aspects, taken in conjunction with the accompanying drawings ofwhich:

FIGS. 1A to 1F are cross-sectional views depicting a fabricating processwherein an amorphous silicon layer is crystallized into apolycrystalline silicon layer using an SGS (Super Grain Silicon)crystallization method according to an aspect of the present invention;

FIG. 2 is a cross-sectional view depicting a polycrystalline siliconlayer formed according to an aspect the present invention after thepolycrystalline silicon layer is etched lightly;

FIG. 3 is a cross-sectional view of a thin film transistor adopting thepolycrystalline silicon layer formed according to an aspect of thepresent invention;

FIG. 4 is a block diagram illustrating an example of a flat paneldisplay device to which the transistor according to an aspect of thepresent invention can be applied; and

FIG. 5 is an equivalent circuit diagram depicting a pixel circuit of aflat panel display device to which the transistor according to an aspectof the present invention can be applied.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to aspects of the presentinvention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to the like elementsthroughout. The aspects are described below in order to explain thepresent invention by referring to the figures.

FIGS. 1A to 1F are cross-sectional views depicting a fabricating processwherein an amorphous silicon layer is crystallized into apolycrystalline silicon layer using an SGS (Super Grain Silicon)crystallization method according to an aspect the present invention.First, FIG. 1A is a cross-sectional view depicting a process duringwhich a buffer layer 102 is formed on a substrate 101, and an amorphoussilicon layer 103 is formed on the buffer layer 102. As shown in FIG.1A, the buffer layer 102 is formed as a single layer or a double layerof a silicon oxide layer or a silicon nitride layer by use of a chemicalvapor deposition technique or process or a physical vapor depositiontechnique or process on the substrate 101. In various aspects, thesubstrate 101 is made of plastic, glass or steel. As shown, the bufferlayer 102 prevents (or reduces) the diffusion of water or impuritiesgenerated from the bottom substrate 101. The buffer layer 102 alsocontrols the velocity of heat transfer so that a semiconductor layer canbe crystallized properly.

Subsequently, the amorphous silicon layer 103 is formed on the bufferlayer 102. In the aspect shown, the amorphous silicon layer 103 isformed by the chemical vapor deposition technique in general, though notrequired. The amorphous silicon layer 103 formed by the chemical vapordeposition technique contains gases such as hydrogen, and the gasescause problems such as a decrease in mobility of electrons, and so on.Accordingly, a dehydrogenation process is executed (or performed) sothat hydrogen is not left in (or is removed from) the amorphous siliconlayer 103.

FIG. 1B is a cross-sectional view depicting a process during which acapping layer 104 is formed on the substrate 101. As shown in FIG. 1B,the capping layer 104 is formed on the substrate 101 on which theamorphous silicon layer 103 is formed. As shown, the capping layer 104is formed of an oxide film or a nitride film by the chemical vapordeposition technique. The oxide film is made of a material such assilicon dioxide (SiO₂), aluminum oxide (such as alumina, Al₂O₃), hafniumoxide (such as HfO₂), and zirconium oxide (such as zirconia, ZrO₂), andthe nitride film is made of a material such as silicon nitride (such asSiNx). In other aspects, the capping layer 104 may be any combinationsof the oxide or nitride films.

As shown, the characteristics of the capping layer 104 can be changed bya variety of processing conditions during the course of the chemicalvapor deposition process, and such characteristics change of the cappinglayer 104 can influence the diffusion or the infiltration of metalcatalysts during the course of subsequent processes and thecrystallization of the amorphous silicon layer 103 significantly. Thatis, when the capping layer 104 is formed by the chemical vapordeposition process, the characteristics of the capping layer 104 can bechanged by changes in key variables such as an amount of silane gas,and/or an amount and power (or pressure) of ammonia gas.

As shown, the capping layer 104 is defined as an insulating layer whichcontributes to the crystallization of the amorphous silicon layer 103.The capping layer 104 controls the concentration or the amount of themetal catalyst by controlling the diffusion and the infiltration of themetal catalyst during the course of one or more heat treatmentprocesses. The capping layer 104 can be made of an oxide such as silicondioxide (SiO₂), aluminum oxide (such as alumina, Al₂O₃), hafnium oxide(such as HfO₂), zirconium oxide (such as zirconia, ZrO₂), or a nitridesuch as silicon nitride (SiNx), or any combinations thereof.

FIG. 1C is a cross-sectional view depicting a process during which ametal catalyst layer 105 is formed on the capping layer 104. As shown inFIG. 1C, the metal catalyst layer 105 is formed by depositing metalcatalysts on the capping layer 104. As shown, the metal catalyst layer105 is formed by depositing one, or more than one metal catalysts of Ni,Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or anycombinations thereof. It is preferable, but not required, to form themetal catalyst layer 105 with Ni because Ni can crystallize theamorphous silicon layer 103 into a polycrystalline silicon layer 110more easily.

FIG. 1D is a cross-sectional view depicting a process during which metalcatalysts 108 c are absorbed or diffused into the capping layer 104 bycarrying out of a first annealing process (depicted as) 106 while thesubstrate 101 undergoes a first heat treatment.

Subsequently, a process during which the amorphous silicon layer 103 iscrystallized as the substrate 101 undergoes the first annealing process106, is carried out. During the first annealing process 106, the metalcatalyst 108 c contained in the metal catalyst layer 105 diffuses orinfiltrates (depicted as) 107 into the capping layer 104, and moves toan interface 104 a between the capping layer 104 and the amorphoussilicon layer 103 (shown in FIG. 1C). Consequently, a crystallizationseed 108 a is formed. As shown, metal catalysts 108 b, which cannotreach the amorphous silicon layer 103, do not influence thecrystallization of the amorphous silicon layer 103 at all. Preferably,the temperature for the heat treatment during the first annealingprocess 106 is 500° C. to 650° C., though not required. If the substrate101 is heat-treated below 500° C., the crystallization cannot beaccomplished as properly (or efficiently). On the contrary, in case thatthe substrate is heat-treated over 650° C., a seed 108 a cannot beformed (or dispersed) as uniformly.

As shown, during the first annealing process 106, the metal catalyst 108c moves to the interface 104 a between the amorphous silicon layer 103and the capping layer 104 as the substrate 101 undergoes the first heattreatment. Subsequently, the crystallization seed (or the seed) 108 a isformed. The amorphous silicon layer 103 is crystallized into a grain 110a of a polycrystalline silicon layer 110 using the seed 108 a byadopting the SGS (Super Grain Silicon) crystallization method.

FIG. 1E is a cross-sectional view depicting a process during which apolycrystalline silicon layer 110 having low concentration of aremaining metal catalyst 108 c is formed by removing the metal catalystlayer 105 and the capping layer 104. As shown in FIG. 1E, thepolycrystalline silicon layer 110 having low concentration of theremaining metal catalyst 108 c is formed by removing the capping layer104. When the capping layer 104 is removed, the seed 108 a formed at theinterface 104 a between the capping layer 104 and the polycrystallinesilicon layer 110 should be removed together in order to form animmaculate (or a clean) interface 104 a.

As shown, a time when the metal catalyst layer 105 and the capping layer104 should be removed is calculated by the following equation 1.

$\begin{matrix}{{V*t} < \frac{L}{2}} & \lbrack {{Formula}\mspace{20mu} 1} \rbrack\end{matrix}$

Here, V is the average crystallization velocity, L is the distancebetween the seeds 108 a, and t is the crystallization time.

That is, it is preferable, but not required, to remove the metalcatalyst layer 105 and the capping layer 104 when a respective grain 110a distance (shown in FIG. 1F) is smaller than half of the averagedistance between the metal catalysts after the amorphous silicon layer103 is crystallized.

For instance, if the grain boundary 110 c grows at the rate of 0.83 μmper minute at 600° C., and the distance between the metal catalysts is20 μm,

$\begin{matrix}{t < {\frac{20\mu \; m}{2}\frac{1}{0.83\mu \; {m/\min}}\mspace{14mu} t} < {12.05\mspace{11mu} \min}} & \lbrack {{Formula}\mspace{14mu} 2} \rbrack\end{matrix}$

That is, it is preferable, but not required, to remove the metalcatalyst layer 105 and the capping layer 104 after the substrate 101undergoes the first heat treatment for about 12 minutes, in thisexample.

FIG. 1F is a drawing depicting a process during which a remainingamorphous silicon layer 103 a is crystallized as the substrate 101undergoes a second annealing process (depicted as) 108 while thesubstrate 101 undergoes a second heat treatment. During the secondannealing process 108, the amorphous silicon layer 103 is crystallizedbeginning with (or starting at) the polycrystalline silicon layer grain110 a formed after the first annealing process 106.

One grain 110 a of polycrystalline silicon layer 110 grows from one seed108 a formed by the metal catalyst 108 c, and when the grains which growfrom a plurality of different seeds (such as 108 a) come in contact withone another, the grain boundary 110 c is formed. Therefore, if theamount of the metal catalysts 108 c which reaches the interface 104 a iscontrolled properly (that is, after the first annealing process 106, thediffusion of the metal catalyst 108 c is controlled by removing theunnecessary metal catalysts 108 c and the capping layer 104,consequently, the number of the seed 108 a for grain growth at theinterface 104 a can be controlled), the grain 110 a of thepolycrystalline silicon layer 110 becomes larger, and the number of thegrain boundary 110 c becomes smaller. Preferably, though not required,the temperature for the second annealing process 108 is 550° C. to 800°C. If the substrate 101 is heat-treated below 550° C., thecrystallization cannot be accomplished as properly (or efficiently). Onthe contrary, in case that the substrate is heat-treated over 800° C.,the substrate can be deformed.

As shown, during the second annealing process 108, the remainingamorphous silicon layer 103 a is crystallized into the polycrystallinesilicon layer 110 formed after the first annealing process 106 (usingthe SGS (Super Grain Silicon) crystallization method) as the substrate101 undergoes the second annealing process 108.

In the polycrystalline silicon layer 110 formed by the SGScrystallization method, the diffusion of the metal catalyst 108 c iscontrolled by removing the unnecessary metal catalyst 108 c and thecapping layer 104 after the first annealing process 106. Therefore, thesecond annealing process 108 is carried out when the number of the seed108 a for grain growth at the interface 104 a is controlled or removed.Consequently, the grain 110 a of the polycrystalline silicon layer 110becomes larger, and the number of the grain boundary 110 c becomessmaller.

FIG. 2 is a microscopic image depicting the polycrystalline siliconlayer 110 formed using the SGS crystallization method according toaspects of the present invention after the polycrystalline silicon layer110 is etched lightly. In the case of the polycrystalline siliconportion 110 b formed by the second annealing process 108, theconcentration of the metal catalyst 108 c is lower, or the crystallinityis better than when the polycrystalline silicon portion (or grain) 110 cformed by the first annealing process 106. This is because the diffusionand infiltration of the unnecessary metal catalyst 108 c is reduced asthe metal catalyst layer 105 and the capping layer 104 are removed afterthe first annealing process 106. As the amount of unnecessary metalcatalyst 108 c is reduced, the crystallinity becomes excellent (orimproved) because the grain (such as 110 a) can be formed uniformly. Invarious aspects, the first heat treatment may nucleate and/or grow thegrain 110 a and the subsequent second heat treatment further grows thegrain 110 a into a larger grain 110 b, which includes grain 110 a. Inother aspects, further independent nucleation of grains is prevented orminimized during the second heat treatment so that the grain 110 asimply grows into the larger grain 110 b.

FIG. 3 is a cross-sectional view of a thin film transistor using thepolycrystalline silicon layer 110 formed using the SGS crystallizationmethod according to aspects of the present invention. As shown in FIG.3, the buffer layer 102 is formed on the substrate 101 made of glass,quartz, plastic, or steel. Subsequently, a silicon layer 111 (an activeregion) is formed by patterning the polycrystalline silicon layer 110after the polycrystalline silicon layer 110 is formed as described inFIGS. 1A to 1F. In the active region 111, the diffusion of the metalcatalyst 108 c is controlled by removing the unnecessary metal catalyst108 c and the capping layer 104 after the first annealing process 106.Accordingly, the second annealing process 108 is carried out when thenumber of the seeds 108 a for grain growth at the interface 104 a iscontrolled. Therefore, the grain 110 a of the polycrystalline siliconlayer 110 becomes larger, and the number of the grain boundary 110 cbecomes smaller. Consequently, even an active region 111 including nograin boundary or at least one grain boundary can be formed.

Subsequently, after a gate insulating layer 112 is formed by forming aninsulating layer (such as a silicon oxide film, a silicon nitride film,or any combination thereof) in a single layer or a double layer, a gateelectrode 113 is formed by depositing and patterning a gate electrodeforming material. As shown, a source/drain region and a channel region(in the active layer 111) can be defined by carrying out an impurityinjection process on the silicon layer 111 (an active region) using thegate electrode 113 as a mask. The gate electrode 113 can be any oneselected from MoW, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy,or any combinations thereof.

Subsequently, a contact hole exposing one or more portions of layers isformed by etching a predetermined region of an inter-layer dielectriclayer 114 and the gate electrode 113, after the inter-layer dielectriclayer 114 is formed by forming an insulating layer (such as a siliconoxide film, a silicon nitride film, or any combinations thereof) in asingle layer or a in a double layer on the entire surface of thesubstrate 101. Then, a thin film transistor 100 is completed as asource/drain electrode (such as 115) is formed by depositing andpatterning a source/drain electrode forming material on the entiresurface of the substrate 101.

The thin film transistor 100 manufactured by the fabricating method soas to have the structure described above can be used widely as aswitching transistor and a driving transistor of a variety of flat paneldisplay devices (such as an active matrix liquid crystal display deviceand an organic light emitting diode display device). Hereinafter, anorganic light emitting diode display device 400 will be described as anexample of the flat panel display device equipped with the transistor100. However, the transistor 100 according to an aspect of the presentinvention is not limited simply to the organic light emitting diodedisplay device 400.

Referring to FIG. 4, an active matrix liquid crystal display device isshown as an example of a flat panel display device to which thetransistor 100 according to an aspect of the present invention can beapplied. As shown in FIG. 4, an organic light emitting diode displaydevice 400 can be integrated and formed including a scan driver 410, adata driver 420, and a pixel portion 430 driven by the scan driver 410and the data driver 420.

Referring to FIG. 5, a pixel portion or a pixel circuit 430 of a flatpanel display device to which the transistor 100 according to an aspectof the present invention can be applied is shown. As shown in FIG. 5, inthe pixel circuit 430, a sub-pixel consists of a scan line (Scan) toselect which pixel 431 should be driven; a data line (Data) to apply acontrolled amount of voltage to the pixel 431 according to a controlledselection; a switching transistor (T1) to control the data flowaccording to a signal of the scan line (Scan); a power source line (VDD)to supply power; a storage capacitor (Cs) to store an electric charge asmuch as (or in the amount of the voltage difference between the voltageapplied from the data line (Data) and the voltage supplied from thepower source line (VDD); a driving transistor (T2) to send an electriccurrent as an electric current is supplied with (or in the amount of thevoltage stored in the storage capacitor (Cs); and an organic lightemitting diode to emit light according to the electric current thatflows through the driving transistor (T2).

In addition, the switching transistor (T1) and the driving transistor(T2) are formed with one PMOS thin film transistor respectively, forexample. The switching transistor (T1) and the driving transistor (T2)can include more than one PMOS and/or NMOS thin film transistorsrespectively according to the characteristics of the function desired.

The switching transistor (T1) and the driving transistor (T2) have thesame structure as the structure of the transistor 100 according to anaspect of the present invention. A leak (or leakage) current can bereduced by minimizing the concentration of the metal catalyst 108 c leftin the silicon layer 111 (an active region) of the transistor 100. Inaddition, a silicon layer 111 of excellent (or improved) crystallinitycan be obtained by reducing the unnecessary crystallization by metalcatalysts 108 c.

Accordingly, the characteristics of a display can be improved byapplying the transistor 100 according to aspects of the presentinvention to a flat panel display device 400 such as an organic lightemitting diode display device and a liquid crystal display device.

As described above, the object of the transistor, the fabricating methodthereof and the flat panel display device therewith according to aspectsof the present invention is to control the concentration of the metalcatalyst left in the polycrystalline silicon layer when an amorphoussilicon layer is crystallized using the SGS crystallization method. Thesubstrate undergoes the first annealing process by absorbing ordiffusing an extremely small amount of the metal catalyst into thecapping layer as the substrate undergoes the first annealing process.Then the substrate undergoes the second annealing process after thecapping layer and the metal catalyst layer are removed. Consequently,the concentration of the metal catalyst left in the polycrystallinesilicon layer can be minimized and a leak (or leakage) current can alsobe minimized.

The above detailed description is one aspect of the transistor which canprevent or reduce a leak (or a leakage) current, the fabricating processthereof and the flat panel display device therewith according to aspectsthe present invention, and the aspects of the present invention is notlimited to these aspects. It will also be understood that when a layeror element is referred to as being “on” or “over” another layer orsubstrate, it can be directly on the other layer or substrate, orintervening layers may also be present. Further, it will be understoodthat when a layer is referred to as being “under” or “below” anotherlayer, it can be directly under, or one or more intervening layers mayalso be present.

Although a few aspects of the present invention have been shown anddescribed, it would be appreciated by those skilled in the art thatchanges may be made in the aspects without departing from the principlesand spirit of the invention, the scope of which is defined in the claimsand their equivalents.

1. A transistor, comprising: a substrate; an active region including asource region, a channel region, and a drain region, which arecrystallized using an SGS (Super Grain Silicon) crystallization methodand are formed on the substrate so that a grain size of a first annealedportion and a second annealed portion are different from each other; agate insulating layer formed on the active region; and a gate electrodeformed on the gate insulating layer.
 2. The transistor as claimed inclaim 1, wherein a grain boundary size of the first annealed portion issmaller than that of the second annealed portion.
 3. The transistor asclaimed in claim 1, wherein the active region includes metal catalysts.4. The transistor as claimed in claim 3, wherein the concentration ofthe metal catalysts in the first annealed portion is higher than that ofthe second annealed portion.
 5. The transistor as claimed in claim 3,wherein the metal catalyst is one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu,Co, Mo, Tr, Ru, Rh, Cd, Pt, or any combinations thereof.
 6. Thetransistor as claimed in claim 1, wherein the source region and thedrain region are doped with a P-type dopant.
 7. The transistor asclaimed in claim 1, wherein the source region and the drain region aredoped with an N-type dopant.
 8. The transistor as claimed in claim 1,wherein the gate electrode is one of MoW, Ti, Cu, AlNd, Al, Cr, Moalloy, Cu alloy, Al alloy, or any combinations thereof.
 9. Thetransistor as claimed in claim 1, further comprising a buffer layerformed between the substrate and the active region.
 10. The transistoras claimed in claim 1, further comprising: an inter-layer dielectriclayer formed on a surface of the gate insulating layer and the gateelectrode; a source electrode connected to the source region andpenetrating through the inter-layer dielectric layer and gate insulatinglayer; and a drain electrode connected to the drain region andpenetrating through the inter-layer dielectric layer and the gateinsulating layer.
 11. The transistor as claimed in claim 1, wherein agrain boundary does not exist in the active region.
 12. The transistoras claimed in claim 1, wherein at least one grain boundary exists in theactive region.
 13. A fabricating method of the transistor, comprising:preparing a substrate, forming an amorphous silicon layer on thesubstrate; forming a capping layer on the amorphous silicon layer;forming a metal catalyst layer on the capping layer; performing a firstannealing process to crystallize amorphous silicon of the amorphoussilicon layer into first annealed polycrystalline silicon using an SGS(Super Grain Silicon) crystallization method wherein metal catalysts ofthe metal catalyst layer diffuse as far as the amorphous silicon bypenetrating through the capping layer; removing the metal catalyst layerand the capping layer; and performing a second annealing process whereinthe metal catalyst crystallizes the amorphous silicon into secondannealed polycrystalline silicon using the SGS crystallization method toform a polycrystalline silicon layer.
 14. The fabricating method of thetransistor as claimed in claim 13, further comprising: forming asemiconductor layer by patterning the polycrystalline silicon layer; andforming a gate insulating layer, a gate electrode, an inter-layerdielectric layer, and a source/drain electrode on the substrate.
 15. Thefabricating method of the transistor as claimed in claim 13, whereinduring the removing of the metal catalyst layer and the capping layer,the metal catalyst layer and the capping layer are removed once theamorphous silicon is crystallized so that a respective grain boundarysize is smaller than half of an average distance between the metalcatalysts.
 16. The fabricating method of the transistor as claimed inclaim 13, further comprising: forming a buffer layer before forming ofthe amorphous silicon layer on the substrate.
 17. The fabricating methodof the transistor as claimed in claim 13, wherein crystallinity of thepolycrystalline silicon formed by the first annealing process isdifferent from that of the polycrystalline silicon formed by the secondannealing process.
 18. The fabricating method of the transistor asclaimed in claim 13, wherein a grain boundary size of thepolycrystalline silicon formed by the first annealing process is smallerthan that of the polycrystalline silicon formed by the second annealingprocess.
 19. The fabricating method of the transistor as claimed inclaim 13, wherein the concentration of the metal catalyst of thepolycrystalline silicon formed by the first annealing process is higherthan that of the metal catalyst of the polycrystalline silicon formed bythe second annealing process.
 20. The fabricating method of thetransistor as claimed in claim 13, wherein a grain boundary does notexist in the second annealed polycrystalline silicon.
 21. Thefabricating method of the transistor as claimed in claim 13, wherein atleast one grain boundary exists in the second annealed polycrystallinesilicon.
 22. The fabricating method of the transistor as claimed inclaim 13, wherein the metal catalyst layer is one of Ni, Pd, Ti, Ag, Au,Al, Sn, Sb, Cu, Co, Mo, Tr, Ru, Rh, Cd, Pt, or any combinations thereof.23. The fabricating method of the transistor as claimed in claim 13,wherein the capping layer is an insulating layer.
 24. The fabricatingmethod of the transistor as claimed in claim 13, wherein the cappinglayer is one of an oxide film, a nitride film, or any combinationsthereof.
 25. The fabricating method of the transistor as claimed inclaim 13, wherein the oxide film is one of silicon dioxide (SiO₂),aluminum oxide (alumina, Al₂O₃), hafnium oxide (HfO₂), zirconium oxide(zirconia, ZrO₂), or any combinations thereof.
 26. A flat panel displaydevice, comprising: the transistor manufactured by the method of claim13.
 27. The method of claim 13, wherein the first annealing processoccurs between about 500° C. to about 650° C. and the second annealingprocess occurs between about 550° C. to about 800° C.